Complementary metal-oxide-semiconductor (CMOS) technology is widely used in integrated circuits (ICs) due to the lower power consumption as compared to previously preferred NMOS or Bipolar IC's. CMOS is so named because it uses both p- and n-channel transistors in its ICs. However, fabricating both p-channel and n-channel transistors on the same IC adds a number of processing steps to the IC fabrication process.
The n-channel devices typically require n+ poly silicon gate material to set the correct turn-on voltage (threshold). The p-channel devices can be either a buried channel or surface channel device depending on whether n+ or p+ poly silicon is used for the gate material. When a p-channel transistor uses the same n+ poly silicon material as the NMOS device, then it is considered to be a buried p-channel device and the subsequent fabrication process becomes cost-effective. As a result, buried p-channel devices were predominantly used in DRAM and SRAM technologies. The disadvantage of buried p-channel devices is that they are slow (lower current drive) and have non-scalable threshold voltages. DRAM's, till recently, decided to stay with the buried p-channel transistors since it kept the rest of the processing in the array and peripheral n-channel transistors simpler. On the other hand, to achieve higher speed and voltage scalability the SRAM's elected to switch to surface p-channel devices. CMOS with surface p-channel transistors, however, needed a hardened gate oxide and two separate formations of gate poly silicon (n+ and p+) resulting in an extra masking step. With the addition of across the die hardened gate oxide, this surface p-channel CMOS design had to settle for slightly degraded n-channel transistors, because only one gate oxide deposition step was practical.
A prior fabrication method used in forming a pair of complementary surface channel CMOS transistors is as follows. First a P-well and an N-well is created in the substrate, then a gate oxide is formed over the complementary wells. To form the gates, an intrinsic poly silicon layer is deposited over the gate oxide. Then, a gate region for the p-channel device is masked over the N-well and the intrinsic poly silicon layer in the p-channel gate region is doped to P-type poly silicon. After doping the p-channel gate region, the mask is removed, and a gate region for the n-channel device is masked over the P-well and the intrinsic poly silicon layer in the n-channel gate region is doped to N-type poly silicon.
One drawback with this method of IC manufacture is that it requires several lithography masking steps. The substrate must be masked while forming the P-well. The substrate must be masked again when forming the N-well. Another masking step is needed to introduce the P-type dopant for the p-channel gate, and a fourth masking step is needed to introduce the N-type dopant for the n-channel gate. Lastly, a fifth masking step is needed to pattern the final gate stack just prior to the isolation step.
In doping the poly silicon gate layer, the dopant can be diffused into the layer by exposure to a dopant atmosphere, or the dopant can be ion implanted. In either case, the concentration profile through the thickness of the doped poly silicon layer varies significantly. This concentration gradient is detrimental to device performance. Gates formed by doping poly silicon tend to form a poly depletion layer near the gate oxide during operation, which causes an increase in effective gate oxide thickness. The dopants introduced to the poly silicon layer are more heavily concentrated in the top surface of the gate region than at the bottom, adjacent the gate oxide. An increase in effective gate oxide thickness can decrease device performance. Therefore, it is preferable to have in-situ doped poly silicon over implanted poly silicon.
Another major disadvantage of this approach, as seen by DRAM's, is that one can no longer rely on conventional source-drain re-oxidation schemes to selectively increase the oxide thickness at the poly gate edges due to the presence of hardened gate oxide. The hardened gate oxide inhibits oxygen diffusion from beneath the gate, which is needed to increase the oxide thickness at the poly gate edges. The DRAM's rely on this step to lower the electric field at the gate-edge and thereby reduce the gate-induced drain leakage (GIDL) in the access transistor.
What is needed is a method of gate formation in CMOS circuits that uses fewer masking steps while still avoiding poly depletion effects. What is also needed is a method of forming gates for CMOS surface channel transistors where the gate dielectrics may be individually tailored for composition and number of layers to perform optimally with the associated gate material.